1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming an isolation of a semiconductor device.
2. Description of Related Art
An isolation region is normally used in a crowded device region of an integrated circuit, such as a dynamic random access memory (DRAM) to prevent carriers moving through neighboring devices, such as field effect transistors (FET). Because the carriers moving through neighboring devices cause charge leakage on the FETs, isolation regions are formed to prevent the occurrence of change leakage. An isolation region normally exists in the form of a thick field oxide layer, and is formed in a semiconductor substrate. Generally, an isolation region is formed by a local oxidation (LOCOS) process. Even though the conventional process, LOCOS, is technically mature, and, reliable and cost-effective isolation regions can be obtained by employing LOCOS process, there are still shortcomings related to this conventional process. The drawbacks related to a LOCOS process includes the formation of bird's beak regions around the field isolation regions. Those drawbacks of the conventional isolation process, especially the formation of bird's beak regions, make it difficult to apply LOCOS process on the fabrication of a higher-integrated semiconductor device.
It is also a conventional method to isolate devices in a integrated circuit by using shallow-trench isolation. Generally, an anisotropic etching process is performed with using silicon nitride as a mask to form steep trenches on a semiconductor substrate. Then, by filling the trenches with oxide, shallow-trench isolations, which have top surfaces are in level with the top surface of the substrate, are formed on the substrate.
FIGS. 1A through 1E are cross-sectional views showing a conventional method forming a shallow-trench isolation.
Referring to FIG. 1A, a oxide 22 is formed on a silicon substrate 10 as a pad oxide layer for protecting the substrate 10, wherein the oxide layer 22 is removed before the formation of a gate oxide layer. A silicon nitride layer 24 is formed on the substrate by performing a chemical vapor deposition (CVD). Then, an etching process is performed on the substrate 10 by using a patterned photoresist layer 28 as a mask to form a trench 30 on the substrate 10, wherein the photoresist layer 28 is removed after the etching process.
Because the stress of the silicon nitride layer 24 is relatively strong, it tends to cause damages on the substrate 10. Therefore, a thick silicon nitride layer 24 leads to the cracking of the substrate 10.
Referring to FIG. 1B, a linear oxide layer 31 is formed in the trench 30 by performing a thermal oxidation process, and then, a silicon oxide layer 32 is filled in the trench 32 and on the surface of the substarte 10.
Referring to FIG. 1C, the oxide layer 32 on the silicon nitride layer 24 is removed by performing a chemical mechanical polishing (CMP) process after a densification process is performed on the oxide layer 32, to form oxide plugs 34. However, the slurry used in the CMP process generates micro scratches 25 on the surface of the oxide plugs that is difficult to be recovered. In addition, a long-period polishing process also tends to cause the dishing problem, which degrades the uniformity of the wafer.
Referring to FIG. 1D, the silicon nitride layer 24 is stripped by using hot phosphoric acid.
Referring next to FIG. 1E, the entire wafer is doused in hydrogen fluoride (HF) for removing the pad oxide layer 22. Even though the oxide plugs 34 are partially removed by the process of removing the pad oxide layer 22, the scratches 35 still remain on the surface of the oxide plugs 34. Those scratches 35 on the surface of the oxide plugs 34 cause bridging defects or even short circuits in the follow-up process that degrades the yield.